1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to adjustment of control signals (such as a clock signal) that define core operations of semiconductor memory elements.
2. Description of the Related Art
An electrically erasable programmable EEPROM, such as a NAND cell-type EEPROM that configures a NAND cell with a plurality of serially connected memory cells, has been known as one of semiconductor memory devices. A memory cell in the NAND cell-type EEPROM has a FETMOS structure with a charge storage layer (floating gate) and a control gate stacked on a semiconductor substrate. The memory cell stores data “0” or “1” depending on the amount of charge accumulated in the floating gate. On data reading, programming (writing) and erasing in the memory cell, such the NAND cell-type EEPROM requires application of voltages to bit lines, word lines and the substrate (or well) with various magnitudes at determined timings depending on situations (see JP-A 2003-208793, pages 4-6, FIG. 4, for example).